An analytical solution to the grain boundary barrier height in undoped polysilicon thin-film transistors

Abstract

Based on U-shaped distribution of density of states (DOS) and discrete grain analysis for grain boundary (GB) traps, a physical-based explicit analytical solution to the GB potential barrier height (Ψ B ) is developed for undoped polycrystalline silicon thin-film transistors (TFTs). The explicit solution is derived by using the Lambert W function, without additional approximations introduced. The validity and accuracy of the solution is demonstrated by comparing the model with both numerical calculations and experimental Ψ B data of polycrystalline Si TFTs.