Energy minimization of 3D cache-stacked processor based on thin-film thermoelectric coolers

Abstract

In this paper, we explore the energy optimization of the processor with 3D stacked cache memory based on thin-film thermoelectric coolers (TFTEC). 3D integrated circuit is suitable for applications requiring small size, high performance and memory capacity. However, 3D integration incurs high power density owing to high temperature and high leakage power. TFTEC as active cooler can be used to deal with high temperature and high leakage energy consumption and eventually to reduce overall energy consumption. Experimental results show that 3D processor with TFTEC achieves a reduction of total energy consumption of both processor and TFTEC by up to 20% compared with processor without TFTEC under a given task's deadline and temperature constraints.