Energy-efficient switching scheme for SAR ADC using zero-energy dual capacitor switching

Abstract

An energy-efficient capacitor switching scheme is presented for a successive approximation register analogue-to-digital converter. The new switching method removes the switching energy loss in the first three comparison cycles and significantly reduces the power consumption in the fourth bit cycle, by combining the negative switching and the energy-efficient up-transition. In addition, a low-power monotonic procedure is implemented for the rest of bit-cycles. The proposed switching technique improves the average switching energy efficiency by 99.31% and reduces the total capacitance size by 75% compared with a conventional binary-search algorithm.