A 99.79% energy saving switching scheme without third reference level and reset energy for SAR ADC

Abstract

An energy-efficient capacitor switching scheme is proposed for successive approximation register analog-to-digital converter. During the design process, the semi-resting DAC structure and charge characteristic of floating capacitor ensure significant energy saving. There is no switching power consumption in the first two comparison process. Compared with the conventional switching scheme, the proposed method decreases 99.79% switching energy and 73.8% capacitor area. Benefit from merge-and-split method, only two reference levels are utilized in this novel scheme, where the power and accuracy of generating the third reference voltage are not necessary to consider. Besides, the reset energy of the proposed scheme is verified to be 0. Furthermore, the common mode voltage at comparator inputs is kept at 0.5Vref except merely a 0.5LSB reduction due to LSB-down technique.