Energy efficient signed and unsigned radix 16 booth multiplier design

Abstract

Low power multiplier unit design is one of Digital Signal Processing (DSP) processors’ requirements to meet the growing demands. Though the higher radix Booth multiplier shows the marginal decrease in the power, the generation of hard multiples in the generation unit becomes the bottleneck in implementing the multiplier unit. This paper proposes an energy-efficient radix-16 Booth multiplier design for combined, signed/unsigned numbers. This paper optimizes the partial product generation unit by (nr−1) (where nrepresents input bit size, and rrepresents radix). As a result, delay and energy reduce significantly. The proposed 16-bit non-pipelined multiplier energy improved by 27.06%,4.35%,and 27.79%,and the pipelined multiplier is improved by 25.74%,31.30%,and 28.42%for signed, unsigned, and combined radix-16 designs respectively.