Abstract
AbstractApproximate computing has been deemed to be an effective way to improve energy efficiency for error‐tolerant applications. In this work, a set of approximate 3‐2, 4‐2, and 5‐2 compressors are proposed by, respectively, introducing specific errors to the truth tables of the exact designs to lower hardware cost. Four 8 × 8 and four 16 × 16 Dadda multipliers are then designed and analyzed using the proposed compressors to achieve a significant optimization in compressing partial products, while keeping an acceptable computing accuracy. Synthesis and simulation results indicate that the proposed 8 × 8 multipliers obtain efficient reductions in area, power, and critical path delay, respectively, by up to 38%, 26%, and 8%, compared with the cutting‐edge designs. An application to the image multiplication algorithm is realized to verify the practicability of the significantly optimized inexact multipliers. Two figures of merits present that the proposed inexact multipliers surpass the counterparts in overall performance embracing hardware cost and computing accuracy in image processing. In this work, a set of approximate 3‐2, 4‐2, and 5‐2 compressors are proposed by respectively introducing specific errors to the truth tables of the exact designs to lower hardware cost. Four 8 × 8 Dadda and four 16 × 16 multipliers are then designed and analyzed using the proposed compressors to achieve a significant optimization in compressing partial products while keeping an acceptable computing accuracy.
Published Version
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