Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory

Abstract

Both computation- and memory-intensiveness of deep learning models have made the deployment of model inference on edge devices with limited resource and energy budget challenging. Non-Volatile Memory (NVM) based in-memory computing has been proposed to reduce data movement as well as energy consumption, which could alleviate the challenge. Racetrack memory is a newly introduced memory technology. It allows high data density fabrication and thus is a good fit for in-memory computing. In order to facilitate the deployment of deep learning models on edge devices, we present an racetrack memory based in-memory integer multiplication, which is one of the core operations in compressed deep learning models. The presented multiplication can be constructed efficiently using racetrack memory technique, and perform the logical operations based on the memory cell with partial reuse of the peripheral circuits. In addition to the multiplication architecture, we also propose and apply a novel write optimization method to the integer multiplication, which transforms the required write operations to shift operations for performance and energy efficiency. The resulting design realizes high area and energy efficiency while maintaining comparable performance with its CMOS counterpart.