Energy-Efficient Digital Front-End Processor for 60 GHz Polar Transmitter

Abstract

This paper presents an energy-efficient digital front-end processor for digital-intensive polar transmitter architecture working on 60 GHz band in standard 28nm CMOS process. This avoids modulating the supply and also eliminates the need of an additional RF limiter and AM detection circuits in the traditional analog-centric polar transmitter architecture. The design challenges on the digital signal processing (DSP) front-end are analyzed and tackled. The systematic optimizations are first explored to minimize the design requirements on the DSP front-end. A pulse shaping filter is designed to shape the frequency spectrum of the quadrature signals so that the signal at the output of the filter is compliant with the spectrum mask requirements. Instead of using computation-intensive raised cosine filter for the pulse shaping, we use poly-phase Cascaded Integrator-Comb (CIC) filter to shape the spectrum. Parallel rotation and vectoring COordinate Rotation DIgital Computers (CORDICs) are designed to perform rectangular-to-polar conversion. Furthermore, a pre-distortion circuit based on look-up table (LUT) is designed to compensate the power amplifier (PA) nonlinearities. Taylor’s approximation is explored to avoid the complex trigonometric computation in the pre-distortion. Finally, an efficient latch-based pipeline is studied to provide the required 7.04 Gsps throughput with less than 60 mW. The synthesis results compare favorably with previously reported architectures.