Abstract
A complete Digital Front-End (DFE) processor for 60 GHz polar transmitter is presented. It avoids supply modulating, RF limiters, and AM detection circuits, compared to traditional analog-centric polar transmitter architectures. The front-end processor consists of i) a poly-phase Cascaded Integrator-Comb (CIC) filter for spectrum shaping; ii) parallel COordinate Rotation DIgital Computer (CORDICs) for rectangular-to-polar conversion; and iii) Power Amplifier (PA) non-linearities pre-distortion units using Look-Up Tables (LUTs). It is designed in two-phase latch-based pipeline to achieve a throughput of 4×1.76 Gsps. Implemented in a standard 28 nm CMOS technology, the DFE processor occupies 0.031 mm2 and consumes 39mW from 0.9V supply. This result outperforms previously reported architectures.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
