ASIC Implementation of Fixed-Point Iterative, Parallel, and Pipeline CORDIC Algorithm

Abstract

In this paper, we proposed a Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of mathematical functions which can be carried out in a wide variety of ways for many digital signal processing applications. The CORDIC is a single unified algorithm for calculating many elementary functions such as trigonometric, hyperbolic, logarithmic function, exponential functions, multiplication, division, and so on. In this paper, a novel low power, low area, and high throughput fixed-point CORDIC algorithms are proposed. The standard CORDIC is also implemented for comparing the synthesis results. The proposed architecture scaling has been done using low area and low-power Scale Factor Correction Unit (SFCU). A low ADP SQRT-CSLA based ADD/SUB unit is proposed to overcomed the disadvantages of the basic ADD/SUB unit used in the standard CORDIC. The ROM lookup table size is also reduced to half. Extensive simulations are performed to verify the functionality. The standard and proposed CORDIC architectures are simulated in cadence NC launch and synthesized in cadence RC tool using TSMC GPDK 45 nm technology and area, power, and delay are calculated. The area and power consumption of the proposed CORDIC architecture are less when compared with standard CORDIC design.