Energy Efficient Design on 16 nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate

Abstract

Scientists in 2010 were using a 40 nanometer Process based FPGA called Virtex-6 and 45 nm Process Technology based FPGA called Spartan-6. After 2010, researchers shifted their focus towards 28 nm technology based 7 series FPGA (Artix-7, Kintex-7, and Virtex-7) due to their intrinsic capability of low power consumption than both 40 nm and 45 nm technology based FPGA. In December, 2013, Xilinx introduced the 20 nm process technology based UltraScale series: Virtex UltraScale and Kintex UltraScale families. But now in 2020, researchers are using 16 nm technology based UltraScale+ FPGA. In our work, we are also using 16 nm technology based UltraScale+ FPGA for implementing our memory using VIVADO 2018.3 hardware programming tool and Verilog Hardware Description Language. There is 49.42%, 25.28% saving in design power on UltraScale+ FPGA when we minimize static probabilities to 0.1 and 0.2 respectively.