VPP - a Verilog HDL simulation and generation library for C++

Abstract

VPP, a Verilog hardware description language (HDL) simulation and generation library for C++, was developed and used by the authors for the firmware design of very large field-programmable gate arrays (FPGAs) with equivalent gate counts of up to 4.4 million for CERN and Fermilab high-energy physics experiments. A C++ program based on the VPP library has the ability to perform behavioral simulation of firmware logic, and is written in syntax very similar to Verilog HDL. Such program can run on any operating system where a C++ compiler is available, and can be easily incorporated into larger system-wide software models. Once the analysis of the firmware model performance is finished, the same unmodified C++ source code is used to automatically generate valid Verilog HDL source code, which then can be converted into FPGA logic by a Verilog HDL synthesis tool. The behavior of that logic will match the initial C++ model exactly.