Energy Efficient Counter Design Using Voltage Scaling on FPGA

Abstract

In this work, we are using voltage scaling to make the counter design as an energy efficient design. The 74163 counter is a 4-bit fully synchronous counter that is available in both TTL and CMOS logic families. In addition to performing the counting function, it can be cleared or loaded in parallel. It has been observed that when different powers have been measured at different frequencies and different voltages in case of counter the significant power dissipation is in case clocks and IOs. Out of which in case of clock the maximum power dissipation is in range of 12.126W to 35.056W at which is in case of 1THz when measured at different voltage levels where as in case of IOs the maximum power dissipation is in range of 20.636W to 25.031W. Which is again in case of 1THz when measured at different voltage levels. There is not much significant change in case of signal and leakage power at different voltage levels. The maximum total power dissipation is in range of 33.887W to 67.986W at frequency of 1THz when operated at different voltages. Also there can be 94.45% to 99.61% reduction in total power dissipation if we operate on frequency of 1MHz instead of frequency of 1THz at different Voltage levels.