Abstract
Ternary content-addressable memory (TCAM) is a hardware search engine that is used to speed up searching through prestored contents rather than addresses. A supplementary don't care (X) state suits TCAM for many network applications but requires a large design area and consumes high power. This brief reports a state-of-the-art architecture of TCAM, which reduces the search (compare) energy dissipation through the adaptive match-line (ML) controller by blocking the evaluation in the subsequent cells when a mismatch or invalid ML data originate in the evaluated cell. The proposed 128 bit $\times$ 32 bit low-energy adaptive associative memory has been implemented using a predictive 45-nm CMOS process and simulated in SPECTRE at a supply voltage of 1 V. The macro area in our proposed architecture has been reduced by 48% compared with the traditional TCAM design with a trivial increment of 13.2% in the energy delay product.
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