Abstract
High Level Synthesis (HLS) tools are enabling non hardware experts to implement applications and algorithms on FPGAs. However, the majority of stream processing application that are currently developed through HLS are implemented statically and they are not exploiting the benefits enabled by partial reconfiguration. In this paper, we propose a generic approach for implementing and using partial reconfiguration through an HLS design flow for Maxeler platforms. Our flow extracts HLS generated HDL code from the Maxeler compilation process in order to implement a static FPGA infrastructure as well as run-time reconfigurable stream processing modules. As a distinct feature, our infrastructure can accommodate multiple partial modules in a pipeline daisy-chained manner, which aligns directly to Maxeler's dataflow programming paradigm. This allows the decomposition of complicated problems into basic building blocks that can be easily stitched together. The basic building blocks are entirely developed using Maxeler's MaxJ language. The benefits of the proposed flow are demonstrated by a case study of a dynamically reconfigurable video processing pipeline delivering 6.4GB/s throughput.
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