Enabling the Design of Behavioral Systems-on-Chip

Abstract

High-Level Synthesis (HLS) dramatically facilitates the design and verification of individual components. These components are typically the dedicated hardware accelerators used within larger systems, e.g. image processing, DSP or encrypheterogeneoustion cores. Unfortunately, HLS is a single process (component) synthesis method. This implies that the integration of these accelerators are often done at the RT-Level, which implies that the system-level verification and co-design needs to be done at lower levels of abstraction. This work presents an approach that enables a path to generate complete SoCs at the behavioral level. Two main contributions that enable this are: First, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses. Second, a library of synthesizable APIs that allow any component in the system to send or receive data through the bus. This approach has significant advantages over traditional approaches. (1) It enables the generation of fast cycle-accurate simulation models of the entire SoC. Experimental results for SoCs of different complexities show that an average speedup of $7.6\times$ is achieved. (2) It allows to completely separate the bus implementation details from the developers view allowing the change between bus types and configuration with only minor changes in the designers’ code. Finally, (3) by creating synthesizable SystemC code any commercial HLS tool can convert the given bus and bus interface code into efficient RTL, thus, making our proposed flow HLS tool agnostic.