Enabling Packaging Architectures and Interconnect Technologies for Image Sensors

Abstract

Abstract Image sensors have become a crucial technology platform for many applications in the past decades. Market demands continue to grow at a fast pace accelerated by innovations, performance improvement, and new applications. Efficient package architectures and advanced interconnect technologies are among the enablers for the commercialization of image sensors. This study examines how image sensor pixel electronics design and form factor drives innovations in chip stacking and high-density interconnects. 3D chip stacking architectures for CMOS image sensors are analyzed. Cases of image sensors for imaging at visible light, single photon avalanche photodiode (SPAD) for wide dynamic range, rolling shutter and global shutter, and depth sensing and light detection and ranging (LiDAR) are explored based on the pixel electronics requirements. Interconnect methods are also explored. Wafer direct bonding followed by through silicon via (TSV) and hybrid bonding technologies have recently been implemented in the image sensor industry. The preferences and challenges of these two interconnect technologies for image sensor chip stacking are discussed. As TSV technology is relatively mature, this study includes the process flow for one example of the hybrid bonding method. Challenges and future advancement are briefed along with the outlook of the technology and market momentum of image sensors.