Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation

Abstract

The objective of post-silicon validation is to identify design errors that remain undetected after pre-silicon verification and, therefore, manifest themselves in the silicon prototypes. These errors are often associated with the subtle interactions between the electrical states of the systems and commonly manifest in the logic domain as bit-flips in flip-flops. They occur under unique operating conditions, which are often not-easily repeatable. In order to shorten the long detection latencies from an error’s occurrence until its observation (i.e., system crash), embedded assertion checkers can be employed. Nonetheless, relying on simulation-based experiments for selecting and assessing the practical effectiveness of a subset of assertion checkers (to be implemented in the physical device) suffers from the slow simulation speed. To address this concern, in this paper, we present a systematic methodology to automatically design emulation-based experiments that can aid the selection and assessment of the embedded assertion checkers. Our results indicate improvements of up to 10% on average for the coverage of flip-flops that are affected by bit-flips when compared with results obtained by simulation-based experiments.