Emulation-based selection and assessment of assertion checkers for post-silicon validation

Abstract

The objective of post-silicon validation is to detect design errors on early silicon prototypes. Electrically-induced errors commonly manifest as bit-flips in the logic domain and they occur under unique operating conditions, which are often not-easily-repeatable. In order to shorten the long detection latencies from an error's manifestation until its observation (i.e. system crash), embedded assertion checkers can be employed. Nonetheless, relying on simulation-based experiments for selecting and assessing the usefulness of a subset of assertion checkers (to be committed to silicon) suffers from limitations associated with the slow simulation speed. To address this concern, in this paper we present a systematic method to automatically design emulation-based experiments that can aid the selection and assessment of the embedded assertion checkers. Our results indicate improvements of up to 10% on average for the coverage of flip-flops that are affected by bit-flips when compared to results obtained from simulation-based experiments.