Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to $\hbox{HfO}_{2}$ and $\hbox{ZrO}_{2}$ Gate Insulators

Abstract

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO2, HfO2, and SiO2 gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (Vth) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in Vth. This effect is also observed in the variance of Vth, due to dopant fluctuation under the gate.