Modeling of Threshold Voltage and Drain Current for Independent Dual-Gate a-InGaZnO Thin-Film Transistors

Abstract

A physics-based threshold voltage and drain current model for the independent dual-gate (DG) a-InGaZnO (a-IGZO) thin-film transistors (TFTs) is presented. The threshold condition of the bottom-gate (BG)-driven device is defined by the ratio of trapped-to-free carrier density at the bottom surface of the channel layer. Thus the developed threshold voltage is related to trap states in the channel layer and the applied top-gate (TG) voltage. The drain current of the device is also modeled based on the calculated Poisson solution and free charge density. Validated by available experiment data, the threshold voltage model gives physical insights and accurate descriptions of current-voltage behaviors for the device in the above-threshold region.