Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors

Abstract

We propose an extraction technique for parasitic resistance (RP) with L-, VGS-, and VDS-dependences even for large VDS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing IDS-VGS characteristics (as a function of VDS ) of two a-IGZO TFTs with different channel lengths ( L1 and L2 ). The resistance between the source and drain is modeled as an effective total resistance defined as RT* ≡ VDS/ID for all over the drain bias VDS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the parasitic resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (VDS') is accurately calculated as a function of VGS, VDS, and L by deembedding the voltage drop across the parasitic resistance RP.