Empirical Measurements of Teledyne CSAC TempCo and Drift Performance

Abstract

Recent advancements in telecom standards and military applications have imposed higher performance specifications on low-SWaP timing solutions. One microsecond timing accuracy during a period on the order of several days to a week is of critical importance. While oscillator performance specifications define frequency error, phase error over temperature cannot be simply calculated or modeled. There is no nominal operating temperature profile for the user community, nor is the TempCo of a Chip-Scale Atomic Clock (CSAC) linear or monotonic. This paper presents measurements of time error under conditions that emulated in-field operation using 22 Teledyne CSACs (TCSAC) and 8 other commercially available low-SWaP atomic clocks. TCSAC phase error was 8.7 ?s on average after 5 days of full operation range temperature cycling. To probe the main sources of phase error, we estimated timing accuracy from TCSAC performance specifications for frequency stability, offset, and drift rate. Predicted time error is of order 100 ?s for similar test conditions when accumulating phase error caused by TempCo and aging. The comparatively low average phase error in test confirmed that TCSAC drift and TempCo can outperform specifications by at least an order of magnitude. The empirical data and theoretical time error calculations are intended to give end-users a useful performance characteristic for the TCSAC in temperature varying environments.