Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach

Abstract

Highly regular multi-processor architecture are suitable for inherently highly parallelizable applications such as most of the image processing domain. System on a programmable chip (SoPC) allows hardware designers to tailor every aspects of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of core, allowing implementation of a multi-processor architecture with an embedded communication network.In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirement and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs. We present both software and hardware implementation with performance results on a Xilinx SoPC target.KeywordsIntegral ImageNormalize Cross CorrelationHomogeneous Transformation MatrixGlobal Movement EstimationGlobal Motion ParameterThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.