Abstract
This paper proposes a structured method for scaling both the supply voltage as well as the body bias voltage for CMOS embedded static memory with the aim of achieving a controllable and dynamic probability of failure with minimum power consumption for each memory block. The target error probability is managed according to the time varying error tolerance attributes of the application using the memory at a certain instant in time. This approach enables system designers to abstract the concepts of power awareness, yield and reliability as design tradeoffs-that incorporate application knowledge-early in the design cycle. The paper develops a formal theoretical and practical foundation based on the underlying device statistics upon which both system and circuit designers can investigate error aware design.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
