Low Power Subthreshold D Flip Flop

Abstract

Energy performance requirements are forcing designers of next-generation systems to explore approaches to least possible power consumption. Scaling of power supply voltage is major factor to reduce the power consumption. Threshold voltage may be reduced to achieve higher drive current and hence better speed, but at the cost of increase in the stand-by power. The technique to achieve ultra low power is to operate the circuit with supply voltage lower than the threshold voltage i.e. subthreshold region. Subthreshold operation is being examined to stretch low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings. Ultra low-power consumption can be achieved by operating digital circuits with scaled supply voltages. In this report proposed subthreshold circuit is based on GDI (Gate Diffusion Input) - a new technique of low power digital combinational circuit design. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design as compared to other CMOS circuits