Abstract
Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.
Highlights
In recent years, the UHV LDMOS has been implemented in power electronics, Microelectromechanical systems (MEMS) domains, power management circuits, and internet of things (IoT) applications [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16]
Four kinds of modulations are used in circular UHV n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) drift-region engineering: (1)
In the first type of modulation, the breakdown voltage increased more than 400 V due to the reduction of the peak electric field and an increase in the
Summary
The UHV LDMOS has been implemented in power electronics, Microelectromechanical systems (MEMS) domains, power management circuits, and internet of things (IoT) applications [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16]. To achieve effective ESD protection, according to the ESD design window shown, there are three important parameters: trigger voltage (Vt1 ), holding voltage (Vh ), and secondary breakdown current (It2 ). If a high-voltage transient is injected into a circuit, the protection device should be turned on to bypass the heavy current in order to avoid core circuit destruction. Vt1prevent of the component usingbeing the transmission-line pulse (TLP) systemlarge voltage/current the circuitbyfrom damaged by the instantaneous to determine whether the protection component can be turned on quickly under a large voltage/current voltage and current transient. The secondary breakdown current is as high as possible because it is defined proposed to suggest where the chip should be protected to reduce the ESD risk [18].
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