Abstract
An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.
Highlights
As semiconductor technology progresses, the functions and efficiency of integrated circuits (ICs) have greatly improved, and microelectronic circuits and power technologies are receiving more attention
HV n-channel lateral diffused MOSFET (nLDMOS) of the Reference device and drift-region modulation devices were measured by a transmission-line pulse (TLP) testing machine, all of measurement results and important physical extracted parameters are presented in Figure 9 and Table 2
The Vh value has a little rising while shrinking the shallow trench isolation (STI) length by 1/4, it will have a significant reduction as the STI length being decreased and the series resistance decreased too
Summary
The functions and efficiency of integrated circuits (ICs) have greatly improved, and microelectronic circuits and power technologies are receiving more attention. Lateral diffused metal–oxide–semiconductor field-effect transistor (LDMOS) devices have been efficiently applied to ICs for power electronics, power managements and display driver, given their advantages of low ON-resistance and ability to withstand high operating voltages [10–16]. The ability of discharging ESD current remains affected by the non-uniform turned-on phenomenon for the multi-finger layout type, which weakens the immunity level per unit device width from ESD for HV LDMOS devices [29–31]. Some improvement techniques embed a silicon-controlled rectifier (SCR) to improve the discharge capability This may cause an LU effect because of its very low holding voltage [32–36]. This study evaluated the effect of different parasitic SCR paths on the ESD immunity of LDMOS related devices. The series resistance characteristics of embedded Schottky diodes in the drain side indicated that this method can effectively increase the It2 value (ESD reliability) of HV nLDMOS devices
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