Abstract
In the present work, we studied Hall effect and resistivity at various temperatures in un-gated and gated MOSFET structures with different high-k gate oxides and buried modulation-doped InAlAs/InGaAs/InP quantum well (QW) channels. Data is obtained on mobility behavior as a function of top semiconductor barrier thickness, carrier concentration, nature of oxide, and annealing. Improvement of Hall mobility has been demonstrated with the increase of top barrier thickness. In the structures with 3nm-thick top barrier the Hall mobility of ~5500 cm2/Vs at room temperature was demonstrated with ALD oxides at sheet densities (1-2)x1012 cm-2. Degradation of mobility with reduction of screening at low carrier density and due to increased coulomb scattering after thermal annealing is demonstrated. Gated Hall measurements allowed to directly obtain mobility vs. carrier density characteristics, and also determine the interface trap density using CV's and Hall concentration data.
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