Abstract
Abstract This paper shows for the first time chip level electron beam probing on fully functional 10nm and 14nm node FinFET chips with sub-fin level resolution using techniques developed in house. Three novel electron beam probing techniques were developed and used in the debug and fault isolation of advanced node semiconductor devices. These techniques were E-beam logic state imaging, electron-beam signal image mapping, and E-beam device perturbation. Two tools that can offer all three techniques were constructed and used in production. The techniques have been successfully applied to real case chip debug and fault isolation on advanced 10nm and 14nm FinFET on production tools developed in-house. Sub-fin level resolution was achieved for the first time.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
