Electromigration Study of Ai/Low K Dielectric Line Structures

Abstract

ABSTRACTElectromigration reliability is a key concern for implementation of low dielectric constant (k) materials for on-chip interconnects. To address this problem, we have carried out a comparative study of electromigration performance for Al(0.5 wt% Cu) line structures formed with TEOS-based SiO2 and a low k polymeric material, poly(arylene ether) (PAE). The test structures consist of 800 μm long single-level ines. Resistometric measurements were performed to determine electromigration lifetime. To supplement lifetime measurements, TEM was used to measure overall grain size and electron back-scatter diffraction (EBSD) was employed to determine the local grain orientation and grain boundary characteristics in the line structure. In addition, SEM was used to examine void morphology. Microstructural analysis revealed a larger grain size and an enhanced (111) texture in PAE-passivated lines compared to TEOS-passivated lines. The differences can be attributed to a high-emperature process used to cure the PAE dielectric. The overall results obtained in this study show reasonably good electromigration performance for low k dielectric interconnects.