Abstract

A coupled electrical–thermal cosimulation with consideration of the temperature dependence of the metal-oxide-semiconductor (MOS) effect is performed for coaxial through silicon vias (C-TSVs) by using equivalent electrical and thermal circuit models. In the equivalent electrical circuit (EEC) model, the dependence of the MOS capacitance on bias voltage, operation frequency, oxide charge density, and temperature is studied, and further verified by measurement results from a previous publication. A 3-D equivalent thermal circuit (ETC) model with lump components, including thermal resistance and thermal capacitance analytically calculated from the geometry and material parameters of C-TSVs, is proposed for transient thermal simulation. The accuracy of the EEC and ETC models is verified by comparisons with full-wave simulations. Transient electrical–thermal co-simulation is performed for the C-TSVs with the EEC and ETC models. Results reveal that the temperature dependence of depletion width and corresponding MOS capacitance leads to considerable variations in the S-parameters of C-TSVs.

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