Electrical properties of phosphorus in situ doped Au-catalyst vapor liquid solid silicon nanowires

Abstract

N-type in-situ doped silicon nanowire-based resistors are fabricated following a CMOS process fabrication. Silicon nanowires are prepared by a Vapour Liquid Solid (VLS) method using gold as the catalyst. The doping level is adjusted by varying the phosphine to silane mole ratio during silicon nanowire growth. A macroscopic electrical model is presented to extract the average silicon nanowire electrical resistivity over a large doping level range (varying from undoped to highly doped nanowires). Carrier transport is strongly affected by the trapping effect of gold impurities into silicon nanowires, and silicon nanowire electrical resistivity is three decades higher than for silicon bulk at low doping levels. The technological requirement in terms of doping level control for the fabrication of devices based on a gold catalyst VLS is demonstrated.