Abstract
In polycrystalline semiconductors the trapping of charge at the grain boundaries has a decisive influence on the electrical transport properties through the formation of electrostatic potential barriers. By proper materials processing many interesting device applications can be realised, which exploit the electrical activity of these interfaces. In this review, the authors describe both the origin and the consequences of the charge capturing at grain boundaries. Special emphasis is given to polycrystalline compound semiconductors, where they summarise the present knowledge on the interface microstructure and its electrical properties. The model of a double Schottky barrier is shown to provide a quantitative basis for understanding the wide range of electrical phenomena in this class of materials. The steady-state current-voltage characteristic becomes highly non-linear through the interplay between the applied bias and the occupation of the defect states at the interface and in the depletion regions. For large potential barriers, high doping levels and elevated bias, large electric fields build up in the depletion regions. This triggers minority carrier generation through impact ionisation by hot majority carriers and strongly enhances the non-linearities in the charge transport. The dynamic electrical properties are probed by AC admittance or pulse measurements and can be traced back to the finite relaxation times of the trapped electron and hole charges. Comparing the experimental results with the theoretical predictions allows one to obtain valuable information on the electronic grain boundary parameters. The relationship between the observed electrical properties and the electronic structure of the junctions is discussed in detail, with ZnO varistors providing the majority of the experimental data. First indications for a general picture of the grain boundary electronic structure appropriate for all compound semiconductors are presented.
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