Abstract
Bottom-gate staggered amorphous indium–gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with Si3N4 and Si3N4/Al2O3 gate dielectrics were fabricated on glass substrates to investigate the electrical instabilities. An anomalous hump was observed only in the Si3N4 device under the positive bias stress. To analyze the anomalous hump, the transmission electron microscope (TEM) images and the two-dimensional (2D) device simulation were investigated, and results showed that insulator thinning and electric field enforcement at the gate edge are not the causes of the hump. In the time dependence of ΔVTH under stress, Si3N4/Al2O3 and Si3N4 devices follow the stretched-exponential and logarithmic time dependences, respectively. That is, in the Si3N4/Al2O3 device, the trapped electrons are spatially redistributed easily in dielectrics or near the interface, which seems to suppress the hump.
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