Electrical Design for the Development of FOWLP for HBM Integration

Abstract

Two unique multi chips Fan-out Wafer Level Package (FOWLP) designs for High Bandwidth Memory (HBM) integration are illustrated here. HBM is a Wide I/O design and requires very high density routing capability which poses a very challenging electrical design problem for the current FOWLP capability. For both the designs, the signal high speed, high density routing and long interconnect length lead to severe signal distortion and interference issues. In the first design, a silicon chip which consists of all the required high density interface routing fabricated using Back End of Line (BEOL) is embedded inside the FOWLP, this is named as Embedded Fine-Pitch Interposer (EFI). For the other design, the high density routing is achieved by the FOWLP Redistribution Layer (RDL) fine line 2µm width/spacing capability.