Electrical characteristics and short channel performance comparison of different gate junctionless transistors

Abstract

This paper describes TCAD simulations of different junctionless transistors with single, double, triple and all-around gate structures at channel length of 15 nm. To explore the optimum design space for four different gate structures, simulations were performed at constant threshold voltage of 0.3 V. From the simulation results, we observed ON to OFF current ratio of the double-gate, triple-gate, and all around-gate devices is approximately 300, 400, and 1400 times that of a single-gate device respectively. The drain induced barrier lowering is effectively suppressed and subthreshold slope is improved by all around-gate structure as compared to other gate structures even at very high channel doping concentration. Gate capacitance of DG, TG and AAG devices are also increased by 23%, 36% and 55% respectively over single gate device. The increase in capacitance is compensated by amount of increase in drain current, hence intrinsic delay of multiple gate devices are lower than single gate device.