Abstract
Using mainly capacitance measurement voltage, time and temperature, we present a characterization of a sheet of defects located near the interface of a Schottky diode. This kind of layer is often observed after technological treatments such as rapid thermal annealing, laser annealing or reactive ion etching. In such a case, a classical DLTS (deep level transient spectroscopy) analysis is partly invalid. We propose a model of the electrical behaviour of such a layer, and we compare it with success to experimental data. The model allows determination of the thickness of the layer, the concentration of the defect, its associated level in the gap of the semiconductor and its capture cross-section vs temperature.
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