Electrical & Physical Characterization of Silicon-Organic Asymmetrical Metal Insulator Semiconductor Capacitive Test Structure

Abstract

To facilitate the assessment of device characteristics including mobility, threshold voltage, on current estimation, device non-uniformity mapping, etc. without the complete fabrication of transistor structures of different channel lengths or specialized test structures with probes inside/outside the channel, we investigate in this work the impact of electrical and physical parameters on the capacitance-voltage (C − V) characteristics of a fundamental two-terminal, Silicon-Organic Asymmetric Metal-Insulator-Semiconductor (SO-AMIS) capacitive structure. The SO-AMIS test structure is a modified rendition of a regular MIS structure in which the top terminal is made considerably smaller than the bottom gate terminal. The C–V characteristics of this exceptionally asymmetric SO-AMIS structure originate due to the dispersion of the charge carriers into the channel and at any given frequency relies upon channel properties. The impact of contact resistance on measured impedance is least as the effective channel length that contributes to measured capacitance is made substantially large by choosing a small measurement frequency and/or large voltage. Two-dimensional numerical simulations results are performed to outline the effect of critical device parameters on the performance of the pentacene based SO-AMIS test structure. Temperature-dependent investigation is additionally conducted to further elaborate the study of the test structure and its model.