Electrical Activity of Defects Induced by Oxygen Precipitation in Czochralski-Grown Silicon Wafers

Abstract

Majority and minority carrier traps introduced in p-type Czochralski-grown silicon (CZ-Si) wafers during two-step low-high temperature annealing procedures were investigated using deep level transient spectroscopy (DLTS). It was determined that the platelike silicon oxide precipitate surface and the punch-out dislocations introduce majority carrier traps having deep energy levels (EV+0.43 eV and EV+0.26 eV, repectively) in the Si band gap in concentrations proportional to the relevant defect density. The minority carrier traps are positioned at EC-0.42 eV and EC-0.22 eV. The majority carrier trap density on the surface of the platelike precipitate was estimated as ∼3×109 cm-2 and the linear trap density for the punch-out dislocations as ∼ 4×104 cm-1.