Efficient VLSI Design Flow

Abstract

The efficient design flow presented in this chapter is a crucial aspect of this work. Full custom design approaches succeed in enabling ultra-low energy operation, but are too time intensive for large-scale digital designs. Commercial standard cell libraries and very-large-scale-integration (VLSI) design flows enable a fast design methodology for large-scale digital designs, but fail to provide ultra-low energy operation. This chapter unifies these two. Chapter 2 presented a logic library which has proven to be performant under ultra-low-voltage variation-sensitive conditions. This chapter takes that logic library to the next level in digital design: a standard cell design flow. The goal is to keep the speed and energy performance of the full custom work referenced in Chap. 2. Until now, it lacked the ease of design, the fast design cycle, the predictability of performance and the optimization methodology of modern standard cell design (tool) flows. This chapter solves just that: the industry-standard commercial tool flow is leveraged to provide logic synthesis, timing analysis, place-and-route and detailed power analysis of the logic library presented in Chap. 2. Register-transfer modelling (RTL) can be used to describe functionality. After the logic library is characterized into logic, timing and power models, the logic synthesis can map the RTL to the logic library. A silicon-ready layout with performance verification can be realized during place-and-route.