Efficient Structures for PLL’s Loop Filter Design in FPGAs in High-Datarate Wireless Receivers – Theory and Case Study

Abstract

In most contemporary phase lock loops (PLLs) used in high-datarate wireless receivers, some or all of the PLL’s components are implemented digitally, in particular the PLL’s loop filter. In this chapter we develop the theory behind new efficient structures for the implementation of loop filters within FPGAs (Field Programmable Gate Arrays) using fixed-point arithmetic. The theory is then investigated via a case study, in which we present FPGA hardware mapping results that show that employing the proposed method results in a decrease of more than 70% in the logic gate count needed as compared to the conventional implementation.