Efficient Realization of CORDIC based LDPC Decoder for WiMax System

Abstract

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance in wired, wireless communication applications and in disk drives. Based on architecture-aware LDPC codes, this paper presents an efficient joint LDPC coding and decoding hardware architecture. We used a special class of quasi-cyclic low-density parity-check (QC-LDPC) codes, which have an efficient encoding algorithm due to the simple structure of their parity-check matrices. Since the parity-check matrix of a QC-LDPC code consists of circulant permutation matrices or the zero matrix, the required memory for storing it can be significantly reduced, as compared with randomly constructed LDPC codes. An encoder and a decoder are designed using Verilog-HDL and are synthesized using synopsys design compiler with ISO nm TSMC standard cell library. We used CORDIC algorithm to implement check node update unit in decoder which saves much hardware compared to conventional LUT approach. We study the optimal permutation of the bit nodes that will result in the maximum possible burst erasure correction capability for a given LDPC code. The simulation results show the burst-erasure correction capability of quasi-cyclic LDPC codes in the IEEE 802.16e (WiMax) standard.