Abstract

Low-power consumption has been always a crucial design constraint for an efficient intellectual property based three-dimensional multi-core system that cannot be ignored easily. As the complexity increases due to the number of cores/stacks/ layers in 3D digital systems, the challenges to handle power can be more difficult at a high abstraction level. Therefore, the low-power approach gives designers an opportunity to estimate and optimize the power consumption in the early stages of design phases. The accurate power estimation through the macro-modeling approach at high-level reduces the risk of redesign cycle and turn-around time. In this research, we have presented an improved statistical macro-modeling approach that estimates power through statistical characteristics of randomly generated input patterns by using Biogeography Based Optimization. These input patterns propagate signals into an IP-based 3D digital test system. In experiments, the test system is based on four 8 to 32- bits heterogeneous cores. The response of the power is monitored by applying the well-known Monte Carlo Simulation technique. The entire power estimation method is performed in two major steps. First, the average power is estimated for an IP-based individual core. Second, the average power for bus-based Through-Silicon-Via is estimated. Finally, the cores and B-TSVs are integrated together to construct a 3D system. Then the average power for complete test systems is estimated. The experimental results of the statistical power macro-model are compared with the commercial Electronic Design Automation power simulator at the operating frequency of 100 MHz. The average percentage error of the test system is calculated as 8.65%. For the validation of these results, the statistical error analysis is additionally performed and reveals that our proposed macro-model is accurate in terms of percentage of error with a feasible amount of time.

Highlights

  • In Very Large Scale Integration (VLSI) design, low-power, performance, and area is a major concern for designers

  • The average power is estimated for an intellectual property (IP)-based individual cores

  • We propose the addition of a new statistical parameter Signal Variance (SV) and its relation with SP and correlation is represented

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Summary

Introduction

In Very Large Scale Integration (VLSI) design, low-power, performance, and area is a major concern for designers. It is difficult for designers to maintain the balance between these. Efficient power macromodeling approach for heterogeneously stacked 3d ICs performance parameters and provide an optimal solution. Low-power consumption has been always a crucial design constraint for an efficient intellectual property (IP)-based threedimensional (3D) multi-core system that cannot be ignored . Nano size of transistor and high operating frequencies increased the cooling cost. 2. Modern portable applications have a battery-life constraint

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