Efficient post-silicon validation via segmentation of process variation envelope — Global vs local variations

Abstract

In this paper, we propose an efficient method for generating validation vectors for identifying delay marginalities under increasing levels of process-variations-across die, across wafers, across wafer lots. With the goal of significantly reducing the number of vectors required for validation, we propose an approach for segmenting the full global plus local process variation envelope into sub-envelopes, where each sub-envelope is guaranteed to capture worst-case full local-only (worst case on-die) and partial global-only (worst case of across die, across wafers, and across wafer lots) variations, and where all sub-envelopes collectively capture the worst-case full global plus local variations. We then use our recent variability aware approach for generating multiple vectors (captured as vector-spaces) in a segment-by-segment manner to guarantee the invocation of the worst-case delay of the chips in the first-silicon batch. We present extensive experimental results to demonstrate the effectiveness of our approach, especially in the context of increasing process variations.