Efficient Memory Error Coding for Space Computer Applications

Abstract

For the secure transaction of data between the central processing unit (CPU) of a satellite on board computer and its local random access memory (RAM), the program memory has been usually designed with Triple Modular Redundancy (TMR), which is a hardware implementation that includes replicated memory circuits and voting logic to detect and correct a faulty value. TMR error correction technique allows single correction of one error bit per stored word. For computers on board a satellite, there is however a definite risk of two error bits occurring within one byte of stored data. In this paper, the application of the quasi-cyclic codes to the routine error protection of SRAM program memory for satellites in low Earth orbit is described and implemented in Field Programmable Gate Array (FPGA) technology. The proposed device is transparent to the routine transfer of data between CPU and its local RAM.