A real time low complexity codec for use in low Earth orbit small satellite missions

Abstract

A single-board computer system created specifically to meet the demands of a new generation of small satellite missions has been designed, built and tested at Surrey Satellite Technology Limited (SSTL). The satellite onboard computer is an MPC8260 based system that was originally developed for use onboard the first Algerian satellite (Alsat-1). For the secure transaction of data between the central processing unit (CPU) of the onboard computer and its local random access memory (RAM), the program memory has been designed with triple modular redundancy (TMR), which is a hardware implementation that includes replicated memory circuits and voting logic to detect and correct a faulty value. TMR error correction technique allows single correction of one error bit per stored word. For computers on board a satellite, there is however a definite risk of two error bits occurring within one byte of stored data. In this paper, a real time low complexity codec for use in low earth orbit small satellite missions is presented and implemented in field programmable gate array (FPGA) technology. The proposed device is transparent to the routine transfer of data between the CPU and its local RAM. A simple method of decoding is adopted that allows considerable simplification of the codec with a low complexity.