Abstract
AbstractThis Letter presents a novel purpose‐designed architecture to realize efficient dual‐port memory structures for image processing applications. The main innovation proposed here is the exploitation of single‐port (SP) sub‐banks to achieve the same data bandwidth offered by a true dual‐port (TDP) memory, but significantly reducing the access time and resources requirement.When compared with a conventional TDP memory bank, the proposed strategy requires up to 25% less silicon area and consumes up to 9% lower power. It also exhibits an access time up to 15% lower.When used within an Actel FPGA RTAX device to realize an image compressor based on the 2D DWT and the SPIHT algorithm, the memory structure proposed here allows reaching an 11 Mpixels/s frame‐rate, which is 77% higher than that achieved by simply instantiating the SP memory banks available on chip. Copyright © 2010 John Wiley & Sons, Ltd.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: International Journal of Circuit Theory and Applications
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.