Abstract
In this article presents an HDL template on the ASIC platform. For quicker and safer image data transmission stable encoding of pictures via image compression and AES through encryption, the DWT was facilitated. The DWT calculation algorithm based on a lifting scheme and a multi-level sub-bands on the ASIC platform are created. 2D-DWTwas built using it. The related sub-bands were chosen to minimize the compression time of the AES encryption, based on compression ratio and data recovery. To ensure high efficiency and latency, the DWT architecture was developedHDL model and AES algorithm for the area, timing and power performance of the ASIC platform have been developed and validated for the DWT architecture. Using 56 nm CMOS technology, the ASIC implementation was carried out.
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