Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs

Abstract

It is known that bus-oriented escape routing and area routing are necessary in a high-speed printed circuit board (PCB) design. In this paper, given a set of global routed buses in a high-speed PCB design, it is assumed that the routed nets in a single bus are represented as a bus-oriented net between two escaped boundary pins. Based on the construction of a virtual wall between two circuit components, the connection transformation of the given bus-oriented nets inside a closed region and the construction of a covering graph for the represented intervals, an iterative modified left-edge algorithm is proposed to minimize the number of the assigned layers and assign all the bus-oriented nets onto the available layers. Compared with Tsai’s algorithm, the experimental results show that our proposed algorithm reduces 15.0% of the layer number and 21.9% of CPU time for six tested examples on the average, respectively. Compared with Chin’s algorithm, the experimental results show that our proposed algorithm use less CPU time to reduce 15.0% of the layer number for six tested examples on the average.